1. Field of the Invention
This invention relates in general to the structure of semiconductor integrated circuits (ICs), and in particular to the structure of a flash memory. More particularly, this invention relates to the structural configuration of a flash memory having a buried channel that is capable of improved programming speed.
2. Description of Related Art
Refer to FIG. 1 of the accompanying drawing. Memory cell unit of a conventional flash memory capable of electrical erasure of the memory content thereof is illustrated schematically in the cross-sectional view. An N-channel transistor for the memory cell of the flash device has its N.sup.+ (such as N.sup.+ polysilicon) gate electrode 130 floating substantially to constitute a surface channel device. The P-type substrate 100 (such as a P.sup.- substrate) has the source region 120 formed as an N-doped region (N.sup.+), and the drain region 110 formed as another N-doped region (N.sup.+) for the cell transistor. An N-type control gate 140 (such as N.sup.+ polysilicon) is formed atop the floating gate 130.
Due to the fact that complementary metal-oxide semiconductor (CMOS) transistors are being widely used in very-large scale integration (VLSI) devices, P-type MOS transistor has become an increasingly important device. However, when designing P-type MOS devices, the doping pattern in the polysilicon gate of the device greatly influences the operating characteristics of the fabricated device.
Thus, in the conventional fabrication technique based on the N-type polysilicon gate, N-type MOS field-effect transistors, hereafter generally referred to as nMOSFET, and pMOSFET are both required to be fabricated by impurity implantation into the P channel of the device so that lower threshold voltage can be used in these VLSI devices. Such implantation fabrication procedures turn pMOSFET into a buried-channel device.
Refer to FIG. 2 of the drawing. A conventional buried-channel pMOSFET 200 has the cross-sectional view illustrating the structural configuration thereof. The buried-channel pMOSFET 200 has an N-doped polysilicon gate 200a formed atop the P-type layer 200b that is used as the implanted and buried P channel.
The structural configuration of the buried-channel pMOSFET similar to the one depicted in FIG. 2 is fabricated in accordance with the structure of the invention to construct the memory cell unit of an electrically erasable and programmable flash memory device.